The standard conversation about Indian semiconductors is about fabs. Whether we have one, when it opens, what node it runs. That conversation is a distraction, because fabrication and design are separate industries and India’s position in them is not remotely the same.

Here is the fact that reframes it. Roughly 20 percent of the world’s semiconductor design engineers work in India, on the order of a lakh or more VLSI engineers, according to industry reporting through 2025.

India has one fifth of the world’s chip designers and close to zero Indian-owned chip architectures.

That is not a talent problem. Talent is the one input India already holds in surplus. The useful question is which input is missing, and it is not the one everybody argues about.

Design and fabrication are different businesses

A modern chip goes through specification, architecture, RTL design, verification, synthesis, place and route, timing closure, physical verification, and then tape-out to a foundry that manufactures it.

Everything before tape-out is design. It needs engineers, software licences and IP. It does not need a fab. This is why fabless companies exist and why Qualcomm, Broadcom, Nvidia and Apple design chips without owning factories.

Fabrication needs a plant costing billions, extreme ultraviolet lithography from a single supplier, and a decade of process learning. It is one of the most capital-intensive activities on earth.

India’s semiconductor mission has approved fabs and packaging facilities and that is real industrial policy with real reasons behind it, including supply chain security. But a fab does not produce design capability. TSMC has never designed a significant chip of its own, deliberately, because its customers would not trust it if it did.

So the fab question and the design question are separate, and India is weak on the design question despite having the workforce.

What those engineers are actually doing

Most of the lakh-plus VLSI engineers in India work in captive centres of foreign companies or in design services firms.

A captive centre is an offshore engineering site of Intel, Qualcomm, AMD, Nvidia, Texas Instruments, Samsung. The engineers are excellent and the work is genuinely hard. The specification comes from elsewhere, the architecture is owned elsewhere, and the resulting product belongs to the parent.

A design services firm sells engineering hours. A client arrives with a specification and the firm executes some portion of the flow. The firm is paid for the work and owns nothing of the outcome.

Both are good businesses employing skilled people. Neither accumulates product ownership. After thirty years you have a very large number of engineers who have executed a great deal of world-class design and a domestic industry that owns very little silicon.

The missing thing is not skill. It is the specification. Whoever decides what the chip should be captures the value, and that decision has consistently been made somewhere else.

The toolchain

The second constraint is structural and less discussed.

You cannot design a modern chip without electronic design automation software. In 2024, Synopsys, Cadence and Siemens EDA held roughly 31, 30 and 13 percent of the global EDA market. Analyses of the sector put the three of them above 90 percent of revenue. Both Synopsys and Cadence reinvest over 30 percent of revenue into research and development, which is what maintaining a full-flow suite costs.

Two consequences follow.

The licences are expensive enough to be a genuine barrier for a startup or a university. This is why chip design entrepreneurship is rarer than software entrepreneurship despite comparable engineering talent, and it is a large part of why so much Indian capability sits inside companies that can afford the tools.

And the toolchain is a control point. When the United States restricted EDA access to China in 2025, the effect was immediate, and the subsequent lifting of those controls moved share prices. A country without domestic EDA is designing at the discretion of another country’s export policy, regardless of how many engineers it has or how many fabs it builds.

There is a third layer above the tools, which is IP. Most chips are assembled from licensed blocks: an Arm core, a PHY, a memory controller. That is efficient and it means the architecture at the heart of the design is somebody else’s. RISC-V changes this in principle, since the instruction set is open, and it is the most interesting development available to a country in India’s position.

So what is missing

Not fabs, though those have their own case. Not engineers.

Product ownership. Companies that decide what to build, carry the risk, and own the result. That requires patient capital on a timeline that deep tech investment in India has historically not offered, because a chip programme is five to seven years to revenue.

Toolchain independence, or at least reduced exposure. Building a competitive full-flow EDA suite from nothing is not realistic. Building strength in specific parts of the flow, and supporting the open-source tool ecosystem that has become genuinely usable for older nodes, is realistic. The open flows are not competitive at leading-edge nodes and they are increasingly adequate for the mature nodes where most chips are actually made.

Architecture capability. Fewer engineers who execute a specification and more who can write one. That is a different skill, learned by owning a product through its full cycle, which requires products to own.

A domestic customer. Indian chips need Indian buyers willing to take integration risk on a first-generation part. Every successful semiconductor industry started with a guaranteed customer, usually defence or telecom procurement.

Why RISC-V is the specific opening

The instruction set architecture is the layer where licensing has been most restrictive and where an open standard changes the economics most directly. India’s Shakti and Vega processor programmes exist and have produced working silicon, which is more than most commentary acknowledges.

The gap between a working academic processor and a commercial product is large and is mostly not about the core. It is verification, software ecosystem, toolchain support, documentation, long-term supply commitments and customer support. That is unglamorous product engineering, it takes years, and it is exactly the kind of work that gets underfunded relative to the demonstration that precedes it.

Which is the same pattern as the gap between a prototype and a product in any other field, at a much larger scale and with a much longer clock.

The short version: India has the engineers and does not have the specification, the tools or the customer. Fabs address none of those three.

The specification is the cheapest of the three to fix, and it gets fixed by companies rather than by policy. Someone has to be willing to own a part for five to seven years before it earns anything. That is a capital problem wearing an engineering costume.

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